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author | Han Gao <rabenda.cn@gmail.com> | 2022-04-28 00:15:35 +0800 |
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committer | Jakov Smolić <jsmolic@gentoo.org> | 2022-04-27 23:18:24 +0200 |
commit | 47b90dedf06234195ea5eb701633396e0acb2687 (patch) | |
tree | 59af8ba5984cb4a5c8dcce4c20d9c5965627efee /sci-libs | |
parent | dev-vcs/git: add USE=selinux for selinux-git policy (diff) | |
download | gentoo-47b90dedf06234195ea5eb701633396e0acb2687.tar.gz gentoo-47b90dedf06234195ea5eb701633396e0acb2687.tar.bz2 gentoo-47b90dedf06234195ea5eb701633396e0acb2687.zip |
sci-libs/openblas: fix riscv detect
Bug: https://bugs.gentoo.org/837806
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Jakov Smolić <jsmolic@gentoo.org>
Diffstat (limited to 'sci-libs')
-rw-r--r-- | sci-libs/openblas/files/openblas-0.3.20-fix-riscv.patch | 116 | ||||
-rw-r--r-- | sci-libs/openblas/openblas-0.3.20.ebuild | 1 |
2 files changed, 117 insertions, 0 deletions
diff --git a/sci-libs/openblas/files/openblas-0.3.20-fix-riscv.patch b/sci-libs/openblas/files/openblas-0.3.20-fix-riscv.patch new file mode 100644 index 000000000000..9a14180cb85d --- /dev/null +++ b/sci-libs/openblas/files/openblas-0.3.20-fix-riscv.patch @@ -0,0 +1,116 @@ +Bug: https://bugs.gentoo.org/837806 +From https://github.com/xianyi/OpenBLAS/pull/3613 + +From 3fc52ebcfb80e01f753938fd314ca07b2c085767 Mon Sep 17 00:00:00 2001 +From: Han Gao <gaohan@uniontech.com> +Date: Wed, 27 Apr 2022 01:34:55 +0800 +Subject: [PATCH 1/2] Fix other arch build in detect. + +When CORE is empty, use -march=loongson3a. Fix it. + +Signed-off-by: Han Gao <gaohan@uniontech.com> +--- + Makefile.system | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile.system b/Makefile.system +index ac60eae5b6..1104893b55 100644 +--- a/Makefile.system ++++ b/Makefile.system +@@ -847,7 +847,7 @@ CCOMMON_OPT += -mabi=32 + BINARY_DEFINED = 1 + endif + +-ifeq ($(CORE), $(filter $(CORE),LOONGSON3R3 LOONGSON3R4)) ++ifneq (, $(filter $(CORE),LOONGSON3R3 LOONGSON3R4)) + CCOMMON_OPT += -march=loongson3a + FCOMMON_OPT += -march=loongson3a + endif + +From 8123324c99ba69ce23b4028468313663001a76c6 Mon Sep 17 00:00:00 2001 +From: Han Gao <gaohan@uniontech.com> +Date: Wed, 27 Apr 2022 02:29:43 +0800 +Subject: [PATCH 2/2] Fix riscv64 arch detect + +Signed-off-by: Han Gao <gaohan@uniontech.com> +--- + cpuid_riscv64.c | 18 +++++++++--------- + getarch.c | 4 ++-- + 2 files changed, 11 insertions(+), 11 deletions(-) + +diff --git a/cpuid_riscv64.c b/cpuid_riscv64.c +index 0eb50e0018..2aa4217816 100644 +--- a/cpuid_riscv64.c ++++ b/cpuid_riscv64.c +@@ -1,5 +1,5 @@ + /***************************************************************************** +-Copyright (c) 2011-2014, The OpenBLAS Project ++Copyright (c) 2011-2022, The OpenBLAS Project + All rights reserved. + + Redistribution and use in source and binary forms, with or without +@@ -13,9 +13,9 @@ modification, are permitted provided that the following conditions are + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. +- 3. Neither the name of the OpenBLAS project nor the names of +- its contributors may be used to endorse or promote products +- derived from this software without specific prior written ++ 3. Neither the name of the OpenBLAS project nor the names of ++ its contributors may be used to endorse or promote products ++ derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +@@ -70,16 +70,16 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + /* or implied, of The University of Texas at Austin. */ + /*********************************************************************/ + +-#define CPU_UNKNOWN 0 +-#define CPU_C910V 1 ++#define CPU_GENERIC 0 ++#define CPU_C910V 1 + + static char *cpuname[] = { +- "UNKOWN", ++ "RISCV64_GENERIC", + "C910V" + }; + + int detect(void){ +- return CPU_UNKNOWN; ++ return CPU_GENERIC; + } + + char *get_corename(void){ +@@ -98,7 +98,7 @@ void get_subdirname(void){ + } + + void get_cpuconfig(void){ +- printf("#define UNKNOWN\n"); ++ printf("#define %s\n", cpuname[detect()]); + printf("#define L1_DATA_SIZE 65536\n"); + printf("#define L1_DATA_LINESIZE 32\n"); + printf("#define L2_SIZE 512488\n"); +diff --git a/getarch.c b/getarch.c +index 4af986fb3b..f4590769d9 100644 +--- a/getarch.c ++++ b/getarch.c +@@ -1731,7 +1731,7 @@ int main(int argc, char *argv[]){ + #ifdef FORCE + printf("CORE=%s\n", CORENAME); + #else +-#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) ++#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) || defined(__riscv) + printf("CORE=%s\n", get_corename()); + #endif + #endif +@@ -1879,7 +1879,7 @@ printf("ELF_VERSION=2\n"); + #ifdef FORCE + printf("#define CHAR_CORENAME \"%s\"\n", CORENAME); + #else +-#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) ++#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) || defined(__riscv) + printf("#define CHAR_CORENAME \"%s\"\n", get_corename()); + #endif + #endif diff --git a/sci-libs/openblas/openblas-0.3.20.ebuild b/sci-libs/openblas/openblas-0.3.20.ebuild index ed4ad9b91ed7..04d90c709e40 100644 --- a/sci-libs/openblas/openblas-0.3.20.ebuild +++ b/sci-libs/openblas/openblas-0.3.20.ebuild @@ -27,6 +27,7 @@ BDEPEND="virtual/pkgconfig" PATCHES=( "${FILESDIR}/${PN}-0.3.12-shared-blas-lapack.patch" + "${FILESDIR}/${PN}-0.3.20-fix-riscv.patch" ) pkg_pretend() { |