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authorJan Beulich <jbeulich@suse.com>2019-11-08 09:04:53 +0100
committerJan Beulich <jbeulich@suse.com>2019-11-08 09:04:53 +0100
commit4a5c67ed841db42c7be13cb2991ece3b3fc4bf75 (patch)
tree1fd1a44252fd896a35508f621c16725163ecd844 /gas
parentx86: convert SReg from bitfield to enumerator (diff)
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x86: convert Control/Debug/Test from bitfield to enumerator
This is to further shrink the operand type representation.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/config/tc-i386.c28
2 files changed, 20 insertions, 14 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b049863619a..1905eb1ba3e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
2019-11-08 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (pi, check_byte_reg, build_modrm_byte,
+ parse_real_register): Use "class" instead of "control"/"debug"/
+ "test" fields.
+
+2019-11-08 Jan Beulich <jbeulich@suse.com>
+
* config/tc-i386.c (pi, check_byte_reg, process_operands,
build_modrm_byte, i386_att_operand, parse_real_register): Use
"class" instead of "sreg" field.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fde8767255c..f31ab390401 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3049,9 +3049,9 @@ pi (const char *line, i386_insn *x)
|| x->types[j].bitfield.regmmx
|| x->types[j].bitfield.regsimd
|| x->types[j].bitfield.class == SReg
- || x->types[j].bitfield.control
- || x->types[j].bitfield.debug
- || x->types[j].bitfield.test)
+ || x->types[j].bitfield.class == RegCR
+ || x->types[j].bitfield.class == RegDR
+ || x->types[j].bitfield.class == RegTR)
fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
if (operand_type_check (x->types[j], imm))
pe (x->op[j].imms);
@@ -6605,9 +6605,9 @@ check_byte_reg (void)
|| i.types[op].bitfield.regmmx
|| i.types[op].bitfield.regsimd
|| i.types[op].bitfield.class == SReg
- || i.types[op].bitfield.control
- || i.types[op].bitfield.debug
- || i.types[op].bitfield.test)
+ || i.types[op].bitfield.class == RegCR
+ || i.types[op].bitfield.class == RegDR
+ || i.types[op].bitfield.class == RegTR)
{
as_bad (_("`%s%s' not allowed with `%s%c'"),
register_prefix,
@@ -7363,7 +7363,7 @@ build_modrm_byte (void)
}
if (flag_code != CODE_64BIT && (i.rex & REX_R))
{
- if (!i.types[!i.tm.opcode_modifier.regmem].bitfield.control)
+ if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
abort ();
i.rex &= ~REX_R;
add_prefix (LOCK_PREFIX_OPCODE);
@@ -7683,9 +7683,9 @@ build_modrm_byte (void)
|| i.types[op].bitfield.regbnd
|| i.types[op].bitfield.regmask
|| i.types[op].bitfield.class == SReg
- || i.types[op].bitfield.control
- || i.types[op].bitfield.debug
- || i.types[op].bitfield.test)
+ || i.types[op].bitfield.class == RegCR
+ || i.types[op].bitfield.class == RegDR
+ || i.types[op].bitfield.class == RegTR)
break;
if (i.types[op].bitfield.regsimd)
{
@@ -10922,9 +10922,9 @@ parse_real_register (char *reg_string, char **end_op)
if ((r->reg_type.bitfield.dword
|| (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
- || r->reg_type.bitfield.control
- || r->reg_type.bitfield.debug
- || r->reg_type.bitfield.test)
+ || r->reg_type.bitfield.class == RegCR
+ || r->reg_type.bitfield.class == RegDR
+ || r->reg_type.bitfield.class == RegTR)
&& !cpu_arch_flags.bitfield.cpui386)
return (const reg_entry *) NULL;
@@ -10965,7 +10965,7 @@ parse_real_register (char *reg_string, char **end_op)
}
if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
- && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
+ && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
&& flag_code != CODE_64BIT)
return (const reg_entry *) NULL;