diff options
author | Nick Clifton <nickc@redhat.com> | 2019-09-10 15:20:58 +0100 |
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committer | Nick Clifton <nickc@redhat.com> | 2019-09-10 15:20:58 +0100 |
commit | aebcfb76fc165795e67917cb67cf985c4dfdc577 (patch) | |
tree | 3c4539161437c15ad09750a9cfc7e0696f3a2986 /bfd/cpu-tilegx.c | |
parent | [PATCH][ARM][GAS]: Support to MVE VCTP instruction. (diff) | |
download | binutils-gdb-aebcfb76fc165795e67917cb67cf985c4dfdc577.tar.gz binutils-gdb-aebcfb76fc165795e67917cb67cf985c4dfdc577.tar.bz2 binutils-gdb-aebcfb76fc165795e67917cb67cf985c4dfdc577.zip |
Enhance the disassembler so that it will reliably determine whether a reloc applies to the middle of the next insn.
PR 24907
binutils* objdump.c (null_print): New function.
(disassemble_bytes): Delete previous_octets local and replace with
a test of the max_reloc_offset_into_insn field of the
bfd_arch_info structure. If a reloc is a potential match for the
next insn, then perform a dummy disassembly in order to calculate
its real length.
bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn
field.
(bfd_default_arch_struct): Initialise the new field.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c: Initialise the new field.
* cpu-alpha.c: Likewise.
* cpu-arc.c: Likewise.
* cpu-arm.c: Likewise.
* cpu-avr.c: Likewise.
* cpu-bfin.c: Likewise.
* cpu-bpf.c: Likewise.
* cpu-cr16.c: Likewise.
* cpu-cr16c.c: Likewise.
* cpu-cris.c: Likewise.
* cpu-crx.c: Likewise.
* cpu-csky.c: Likewise.
* cpu-d10v.c: Likewise.
* cpu-d30v.c: Likewise.
* cpu-dlx.c: Likewise.
* cpu-epiphany.c: Likewise.
* cpu-fr30.c: Likewise.
* cpu-frv.c: Likewise.
* cpu-ft32.c: Likewise.
* cpu-h8300.c: Likewise.
* cpu-hppa.c: Likewise.
* cpu-i386.c: Likewise.
* cpu-ia64.c: Likewise.
* cpu-iamcu.c: Likewise.
* cpu-ip2k.c: Likewise.
* cpu-iq2000.c: Likewise.
* cpu-k1om.c: Likewise.
* cpu-l1om.c: Likewise.
* cpu-lm32.c: Likewise.
* cpu-m10200.c: Likewise.
* cpu-m10300.c: Likewise.
* cpu-m32c.c: Likewise.
* cpu-m32r.c: Likewise.
* cpu-m68hc11.c: Likewise.
* cpu-m68hc12.c: Likewise.
* cpu-m68k.c: Likewise.
* cpu-m9s12x.c: Likewise.
* cpu-m9s12xg.c: Likewise.
* cpu-mcore.c: Likewise.
* cpu-mep.c: Likewise.
* cpu-metag.c: Likewise.
* cpu-microblaze.c: Likewise.
* cpu-mips.c: Likewise.
* cpu-mmix.c: Likewise.
* cpu-moxie.c: Likewise.
* cpu-msp430.c: Likewise.
* cpu-mt.c: Likewise.
* cpu-nds32.c: Likewise.
* cpu-nfp.c: Likewise.
* cpu-nios2.c: Likewise.
* cpu-ns32k.c: Likewise.
* cpu-or1k.c: Likewise.
* cpu-pdp11.c: Likewise.
* cpu-pj.c: Likewise.
* cpu-plugin.c: Likewise.
* cpu-powerpc.c: Likewise.
* cpu-pru.c: Likewise.
* cpu-riscv.c: Likewise.
* cpu-rl78.c: Likewise.
* cpu-rs6000.c: Likewise.
* cpu-rx.c: Likewise.
* cpu-s12z.c: Likewise.
* cpu-s390.c: Likewise.
* cpu-score.c: Likewise.
* cpu-sh.c: Likewise.
* cpu-sparc.c: Likewise.
* cpu-spu.c: Likewise.
* cpu-tic30.c: Likewise.
* cpu-tic4x.c: Likewise.
* cpu-tic54x.c: Likewise.
* cpu-tic6x.c: Likewise.
* cpu-tic80.c: Likewise.
* cpu-tilegx.c: Likewise.
* cpu-tilepro.c: Likewise.
* cpu-v850.c: Likewise.
* cpu-v850_rh850.c: Likewise.
* cpu-vax.c: Likewise.
* cpu-visium.c: Likewise.
* cpu-wasm32.c: Likewise.
* cpu-xc16x.c: Likewise.
* cpu-xgate.c: Likewise.
* cpu-xstormy16.c: Likewise.
* cpu-xtensa.c: Likewise.
* cpu-z80.c: Likewise.
* cpu-z8k.c: Likewise.
gas * testsuite/gas/arm/pr24907.s: New test.
* testsuite/gas/arm/pr24907.d: Expected disassembly.
Diffstat (limited to 'bfd/cpu-tilegx.c')
-rw-r--r-- | bfd/cpu-tilegx.c | 51 |
1 files changed, 21 insertions, 30 deletions
diff --git a/bfd/cpu-tilegx.c b/bfd/cpu-tilegx.c index cfe08b3f9a6..633dde8d970 100644 --- a/bfd/cpu-tilegx.c +++ b/bfd/cpu-tilegx.c @@ -22,36 +22,27 @@ #include "bfd.h" #include "libbfd.h" +#define N(BITS, NUMBER, PRINT, DEFAULT, NEXT) \ + { \ + BITS, /* Bits in a word. */ \ + BITS, /* Bits in an address. */ \ + 8, /* Bits in a byte. */ \ + bfd_arch_tilegx, \ + NUMBER, \ + "tilegx", \ + PRINT, \ + 3, /* Section alignment power. */ \ + DEFAULT, \ + bfd_default_compatible, \ + bfd_default_scan, \ + bfd_arch_default_fill, \ + NEXT, \ + 0 /* Maximum offset of a reloc from the start of an insn. */ \ + } + const bfd_arch_info_type bfd_tilegx32_arch = - { - 32, /* 32 bits in a word */ - 32, /* 32 bits in an address */ - 8, /* 8 bits in a byte */ - bfd_arch_tilegx, - bfd_mach_tilegx32, - "tilegx32", - "tilegx32", - 3, - FALSE, - bfd_default_compatible, - bfd_default_scan, - bfd_arch_default_fill, - 0, - }; + N (32, bfd_mach_tilegx32, "tilegx32", FALSE, NULL); const bfd_arch_info_type bfd_tilegx_arch = - { - 64, /* 64 bits in a word */ - 64, /* 64 bits in an address */ - 8, /* 8 bits in a byte */ - bfd_arch_tilegx, - bfd_mach_tilegx, - "tilegx", - "tilegx", - 3, - TRUE, - bfd_default_compatible, - bfd_default_scan, - bfd_arch_default_fill, - &bfd_tilegx32_arch, - }; + N (64, bfd_mach_tilegx, "tilegx", TRUE, &bfd_tilegx32_arch); + |