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path: root/target-mips/helper.c
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* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
* Convert references to logfile/loglevel to use qemu_log*() macrosaliguori2009-01-151-25/+14
* target-mips: fix indentationaurel322009-01-141-19/+19
* target-mips: get rid of tests on env->user_mode_onlyaurel322009-01-121-220/+223
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
* Fix remaining compiler warnings for mips targets.ths2008-12-201-4/+0
* Fix Xcontext fill, by Here Poussineau.ths2008-09-211-1/+1
* Less hardcoding of TARGET_USER_ONLY.ths2008-07-231-221/+215
* More efficient target register / TC accesses.ths2008-06-271-15/+15
* Fix infinite loop when invalidating TLB, by Herve Poussineau.ths2008-03-291-1/+1
* Handle some more exception types.ths2008-01-041-29/+43
* Fix exception debug output.ths2008-01-031-39/+36
* De-cruft exception definitions, and implement nicer debug output.ths2007-12-261-11/+53
* Improved PABITS handling, and config register fixes.ths2007-12-251-3/+2
* Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.ths2007-11-221-4/+4
* Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths2007-11-081-8/+8
* Fix logic bug which broke TLBL/TLBS handling somewhat.ths2007-10-291-3/+3
* Implement missing MIPS supervisor mode bits.ths2007-10-281-3/+3
* Replace is_user variable with mmu_idx in softmmu core,j_mayer2007-10-141-4/+4
* Fix off-by-one in address check.ths2007-10-131-11/+8
* Code provision for n32/n64 mips userland emulation. Not functional yet.ths2007-09-301-8/+8
* Supervisor mode implementation, by Aurelien Jarno.ths2007-09-291-27/+34
* hflags computation cleanup, by Aurelien Jarno.ths2007-09-261-7/+3
* Optimise instructions accessing CP0, by Aurelien Jarno.ths2007-09-251-0/+3
* Per-CPU instruction decoding implementation, by Aurelien Jarno.ths2007-09-241-6/+3
* find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the...ths2007-09-171-1/+1
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-3/+3
* Partial support for 34K multithreading, not functional yet.ths2007-09-061-27/+30
* Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths2007-08-261-3/+6
* MIPS64 improvements, based on a patch by Aurelien Jarno.ths2007-06-251-3/+3
* Handle MIPS64 SEGBITS value correctly.ths2007-06-231-13/+12
* Handle PX/UX status flags correctly, by Aurelien Jarno.ths2007-05-281-0/+3
* The 24k wants more watch and srsmap registers.ths2007-05-231-1/+1
* Full MIPS64 MMU implementation, by Aurelien Jarno.ths2007-05-131-5/+46
* MMU code improvements, by Aurelien Jarno.ths2007-05-131-12/+10
* MIPS TLB style selection at runtime, by Herve Poussineau.ths2007-05-131-31/+41
* Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno.ths2007-05-091-5/+57
* MIPS 64-bit FPU support, plus some collateral bugfixes in theths2007-05-071-0/+3
* Clear BD slot on next exception if appropriate.ths2007-05-071-0/+4
* Another fix for CP0 Cause register handling.ths2007-04-131-1/+1
* cpu_get_phys_page_debug should return target_phys_addr_tj_mayer2007-04-071-2/+2
* Fix handling of ADES exceptions.ths2007-04-061-1/+3
* fix branch delay slot cornercases.ths2007-04-051-1/+1
* Handle EBase properly.ths2007-04-051-1/+1
* Squash logic bugs while they are fresh...ths2007-03-301-1/+0
* Sanitize mips exception handling.ths2007-03-301-25/+20
* Fix BD flag handling, cause register contents, implement some more bitsths2007-03-181-3/+11
* Replace TLSZ with TARGET_FMT_lx.ths2007-02-201-6/+6
* Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths2007-02-181-1/+1
* Fix PageMask handling, second part.ths2007-01-221-14/+33