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* target-arm : fix thumb2 parallel add/sub opcode decodingChih-Min Chao2010-07-201-2/+2
| | | | | | Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit ed89a2f1b11db03fbdb0ddab93c25913a16c0374)
* ARM atomic ops rewritePaul Brook2009-11-221-85/+165
| | | | | | Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: Paul Brook <paul@codesourcery.com>
* ARM FP16 supportPaul Brook2009-11-191-0/+85
| | | | | | Implement the ARM VFP half precision floating point extensions. Signed-off-by: Paul Brook <paul@codesourcery.com>
* target-arm: use native tcg-ops for ror/bic/vornAurelien Jarno2009-10-271-38/+14
| | | | | Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix neon vsri, vshl and vsli opsJuha Riihimäki2009-10-271-14/+18
| | | | | | | | | | | | Shift by immediate value is incorrectly overwritten by a temporary variable in the processing of NEON vsri, vshl and vsli instructions. This patch has been revised to also include a fix for the special case where the code would previously try to shift an integer value over 31 bits left/right. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: allow modifying vfp fpexc en bit onlyJuha Riihimäki2009-10-271-0/+3
| | | | | | | | | | | | | | | | All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: add support for neon vld1.64/vst1.64 instructionsJuha Riihimäki2009-10-271-52/+81
| | | | | | | | | | | Add support for NEON vld1.64 and vst1.64 instructions. This patch is revised to follow more closely the specification and raises undefined exception if 64bit element size is used for vld2/vst2 or vld4/vst4 instructions. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix neon vshrn/vrshrn opsJuha Riihimäki2009-10-271-9/+3
| | | | | | | | | | | | | In the existing code shift value is clobbered during the pass loop. This patch changes the code so that it stores the intermediate result in the target neon register directly and eliminates the need to use a temporary to hold the intermediate value thus leaving the shift value in the temporary variable intact. This is a new patch in this version of the patch series. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix incorrect temporary variable freeingJuha Riihimäki2009-10-261-2/+2
| | | | | | | | | | tmp4 and tmp5 temporary variables are allocated using tcg_const_i32 but incorrectly released using dead_tmp which will cause resource leak tracking to report false leaks. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: optimize thumb 32-bit multiplyJuha.Riihimaki@nokia.com2009-10-231-17/+1
| | | | | | | | | | Current implementation of thumb mul instruction is implemented as a 32x32->64 multiply which then uses only 32 least significant bits of the result. Replace that with a simple 32x32->32 multiply. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: cleanup internal resource leaksJuha Riihimäki2009-10-231-27/+89
| | | | | | | | | | | Revised patch for getting rid of tcg temporary variable leaks in target-arm/translate.c. This version also includes the leak patch for gen_set_cpsr macro, now converted as a static inline function, which I sent earlier as a separate patch on top of this patch. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330edAurelien Jarno2009-10-181-5/+7
| | | | | | | Use load_reg_var() instead of accessing cpu_R[rn] directly to generate correct code when rn = 15. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7Aurelien Jarno2009-10-181-3/+3
| | | | | | | Use load_reg_var() instead of accessing cpu_R[rn] directly to generate correct code when rn = 15. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: remove cpu_T for ARM once and for allFilip Navara2009-10-171-26/+0
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert VFP not to use cpu_TFilip Navara2009-10-171-28/+22
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert disas_iwmmxt_insn not to use cpu_TFilip Navara2009-10-171-252/+219
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert disas_dsp_insn not use cpu_TFilip Navara2009-10-171-39/+20
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert disas_neon_ls_insn not to use cpu_TFilip Navara2009-10-171-33/+34
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert disas_neon_data_insn and helpers not to use cpu_TFilip Navara2009-10-171-296/+271
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_TFilip Navara2009-10-171-41/+56
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: replace thumb usage of cpu_T registers by proper register ↵Filip Navara2009-10-171-129/+139
| | | | | | | | | | | | allocations The goal is eventually to get rid of all cpu_T register usage and to use just short-lived tmp/tmp2 registers. This patch converts all the places where cpu_T was used in the Thumb code and replaces it with explicit TCG register allocation. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix TANDC and TORC instructionsFilip Navara2009-10-171-0/+2
| | | | | | | Uninitialized register was used instead of proper TCG variable. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCGFilip Navara2009-10-171-9/+142
| | | | | | | | | | | The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16 helpers used fixed registers to return values. This patch replaces that with TCG code, so T0/T1 is no longer directly used by the helper functions. Bugs in the gen_neon_unzip register load code were also fixed. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert gen_lookup_tb not to use cpu_TFilip Navara2009-10-171-2/+1
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: get rid of gen_set_psr_T0 and replace it by ↵Filip Navara2009-10-171-20/+24
| | | | | | | gen_set_psr/gen_set_psr_im Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: fix SRS/RFE instructionsFilip Navara2009-10-171-15/+16
| | | | | | | | | | | The encoding of 'IA' and 'DB' conditions was swapped. SRS instruction must store banked SPSR instead of CPSR at the specific address. Missing 'return' statement at the end of RFE handling. Fixed write-back code to reference correct registers. From: Hyeonsung Jang <hsjang@ok-labs.com> Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: remove unused gen_movl_T2_reg functionFilip Navara2009-10-171-5/+0
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: remove useless line that sets register that is never used againFilip Navara2009-10-171-1/+0
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: get rid of temporary variable cacheFilip Navara2009-10-171-28/+3
| | | | | | | The temporary variable cache in no longer need since tcg_temp_free was introduced. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: use tcg_global_mem_new_i32 to allocate registersFilip Navara2009-10-171-17/+23
| | | | | | | | | | Currently each read/write of ARM register involves a LD/ST TCG operation. This patch uses TCG memory-backed registers to represent the ARM register set. With memory-backed registers the LD/ST operations are transparently generated by TCG and host registers could be used to optimize the generated code. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix sys-queue.h conflict for goodBlue Swirl2009-09-121-2/+2
| | | | | | | | | | | | | | | Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Remove unused gen_bx_T0 function.Filip Navara2009-06-241-8/+0
| | | | | Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* fix ARMv7 data processing instructionsJuha Riihimäki2009-05-151-13/+26
| | | | | | | | | | | | ARMv7 defines a new behavior for ARM data processing instructions compared to earlier architecture revisions; when the destination register is R15, a Branch and Exchange operation is executed rather than a simple Branch to the target address. This patch corrects the behavior of the emulation for the aforementioned operations. To be applied after applying the previous patch in this patch set. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Paul Brook <paul@codesourcery.com>
* fix ARMv7 data processing instructionsJuha Riihimäki2009-05-151-77/+111
| | | | | | | | | | Modernize parts of target-arm/translate.c in preparation for the modifications in the subsequent patch in this patch set. This is done in order to avoid writing new code to target-arm/translate.c that would use deprecated methods and/or variables. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Paul Brook <paul@codesourcery.com>
* Add new command line option -singlestep for tcg single stepping.aurel322009-04-051-0/+1
| | | | | | | | | | | | | | This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix ARM quadword VDUP (core register).pbrook2009-03-171-4/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: rename bswap_i32/i64 functionsaurel322009-03-131-6/+6
| | | | | | | | Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
* global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori2009-01-151-1/+1
| | | | | | | | | | | | These are references to 'loglevel' that aren't on a simple 'if (loglevel & X) qemu_log()' statement. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert references to logfile/loglevel to use qemu_log*() macrosaliguori2009-01-151-4/+4
| | | | | | | | | | | | This is a large patch that changes all occurrences of logfile/loglevel global variables to use the new qemu_log*() macros. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
| | | | | | | | | | The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement (very) basic Thumb2-EE support. This doesn't actually implementpbrook2008-12-191-0/+75
| | | | | | | | | | EE state, just the associated system coprocessor registers. It is sufficient to keep OS setup and context switching code happy. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6104 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix VFP fixed point conversion routines.pbrook2008-12-191-8/+12
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard).balrog2008-12-071-3/+3
| | | | | | | | | | | | This fixes the destination and accumulator registers for the smmul and smmla instructions. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5913 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM: fix usad8 and usada8 usage of registers (Mans Rullgard).balrog2008-12-071-3/+3
| | | | | | | | | | | This fixes the destination and accumulator registers for the usad8 and usada8 instructions. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5912 c046a42c-6fe2-441c-8c8c-71466251a162
* Patch holes in ARM translation (Laurent Desnogues).balrog2008-12-071-2/+4
| | | | | | | | | | | | | | | | | - gen_set_CF_bit31: use the right value to set carry flag - shifter_out_im: remove a spurious semi-colon - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN size 2 case - sbfx, ubfx are v6t2 instructions The correct cps user mode behaviour is unclear so it's left out from the commit until ARM decides it. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5908 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM: cosmetics (Laurent Desnogues).balrog2008-12-071-29/+1
| | | | | | | | | | | | - remove macros that are not used - remove disass structure is_mem field which value is never used - correct a typo in a comment. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5907 c046a42c-6fe2-441c-8c8c-71466251a162
* Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori2008-11-251-2/+2
| | | | | | | | | | | | | This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the code and also fixing a use after release issue in cpu_break/watchpoint_remove_all. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove premature memop TB terminations (Jan Kiszka)aliguori2008-11-181-6/+0
| | | | | | | | | | | | | Now that we can properly restore the pc on watchpoint hits, there is no more need for prematurely terminating TBs if watchpoints are present. Remove all related bits. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5742 c046a42c-6fe2-441c-8c8c-71466251a162
* Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori2008-11-181-4/+5
| | | | | | | | | | | | | | | | | | | | | This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the succeeding enhancements this series comes with. First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching to dynamically allocated data structures that are kept in linked lists. This also allows to return a stable reference to the related objects, required for later introduced x86 debug register support. Breakpoints and watchpoints are stored with their full information set and an additional flag field that makes them easily extensible for use beyond pure guest debugging. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162