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path: root/target-arm/op_helper.c
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* target-arm: use native tcg-ops for ror/bic/vornAurelien Jarno2009-10-271-8/+0
| | | | | Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCGFilip Navara2009-10-171-58/+0
| | | | | | | | | | | The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16 helpers used fixed registers to return values. This patch replaces that with TCG code, so T0/T1 is no longer directly used by the helper functions. Bugs in the gen_neon_unzip register load code were also fixed. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-011-1/+1
| | | | | | | | | | | | In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Get rid of _t suffixmalc2009-10-011-1/+1
| | | | | | | Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-arm: don't use T[x] in helperaurel322009-04-071-1/+1
| | | | | | (Torbjörn Andersson) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7034 c046a42c-6fe2-441c-8c8c-71466251a162
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
| | | | | | | | | | The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove FORCE_RET() and RETURN()aurel322008-12-071-5/+0
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix undeclared symbol warnings from sparseblueswir12008-10-261-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix ARM NEON vdup and vtbl bugs.pbrook2008-09-221-1/+1
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5286 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues).balrog2008-07-191-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | helper.c - copy reference c0_c2 to runtime c0_c2 and not c0_c1 op_helper.c - remove old code (PARAM1, probably some left over from old dyngen) that broke do_[us]sat translate.c - gen_smul_dual should sign-extend from 16 bit to 32 bit and not from 8 to 32 - disas_arm_insn: * smlalxy: that was completely wrong; now the addition is performed as for smlald * pkhtb: optional ASR not taken into account (similar * to [us]sat) * pkhtb/pkhbt: tmp2 is dead * smlald, smlsld, smuad, smusd, smlad, smlsd: rd * and rn swapped git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4898 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka.ths2008-07-031-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix off-by-one unwinding error.pbrook2008-05-251-5/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM N=Z=1 flag fix.pbrook2008-04-011-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 14/16.pbrook2008-03-311-1/+116
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 13/16.pbrook2008-03-311-7/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 12/16.pbrook2008-03-311-0/+148
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 10/16.pbrook2008-03-311-188/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 9/16.pbrook2008-03-311-0/+33
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 8/16.pbrook2008-03-311-0/+23
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4145 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 7/16.pbrook2008-03-311-0/+67
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM TCG conversion 4/16.pbrook2008-03-311-0/+66
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
* fixed invalid typebellard2007-11-111-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
* ARMv7 support.pbrook2007-11-111-2/+76
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
* Adjust s390 addresses (the MSB is defined as "to be ignored").ths2007-10-291-1/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
* Replace is_user variable with mmu_idx in softmmu core,j_mayer2007-10-141-2/+2
| | | | | | | | | | | | | | allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
* Add Arm926 core support.pbrook2006-02-201-5/+7
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1765 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM system emulation (Paul Brook)bellard2005-11-261-0/+51
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
* arm vfp fcmp and fcmpe instructions fix (Paul Brook)bellard2005-04-231-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1382 c046a42c-6fe2-441c-8c8c-71466251a162
* soft float supportbellard2005-03-131-100/+45
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1337 c046a42c-6fe2-441c-8c8c-71466251a162
* ARM VFP support (Paul Brook)bellard2005-02-221-0/+229
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162