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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-10-22 21:42:54 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-10-22 21:42:54 +0000
commita47f43d2723eafc72ea19970af7d8c47baa7220b (patch)
tree8079a091be73c2a8ab54f33e9c18b26cffa1aeff /target-arm/translate.c
parentFix ARMv6t2 strex instructions. (diff)
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Additional exclusive load/store instruction are v6K, not v6T2.
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5518 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 452016cfa..ce3509d45 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6227,7 +6227,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
/* load/store exclusive */
op1 = (insn >> 21) & 0x3;
if (op1)
- ARCH(6T2);
+ ARCH(6K);
else
ARCH(6);
gen_movl_T1_reg(s, rn);