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| author |   Armin Rigo <arigo@tunes.org> | 2020-04-01 10:11:43 +0200 |
|---|---|---|
| committer | Armin Rigo <arigo@tunes.org> | 2020-04-01 10:11:43 +0200 |
| commit | f58ba740ec8bdaf8a02da6c8eb5baf59463b266b (patch) | |
| tree | db6305e6d20b2c6b9ed03a83848b0694b63b6434 | |
| parent | fix for test_short_result_of_call_compiled on ppc: clamp the result values of (diff) | |
| download | pypy-f58ba740ec8bdaf8a02da6c8eb5baf59463b266b.tar.gz pypy-f58ba740ec8bdaf8a02da6c8eb5baf59463b266b.tar.bz2 pypy-f58ba740ec8bdaf8a02da6c8eb5baf59463b266b.zip | |
probable fix for ppc
| -rw-r--r-- | rpython/jit/backend/ppc/opassembler.py | 1 | ||||
| -rw-r--r-- | rpython/jit/backend/ppc/regalloc.py | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/rpython/jit/backend/ppc/opassembler.py b/rpython/jit/backend/ppc/opassembler.py index d481adac9e..b79b18e530 100644 --- a/rpython/jit/backend/ppc/opassembler.py +++ b/rpython/jit/backend/ppc/opassembler.py @@ -757,6 +757,7 @@ class FieldOpAssembler(object): # mc.addi() would not be valid with operand r0. assert ofs_loc.is_imm() # must be an immediate... assert _check_imm_arg(ofs_loc.getint()) # ...that fits 16 bits + assert index_loc.is_core_reg() assert index_loc is not r.SCRATCH2 # (simplified version of _apply_scale()) if ofs_loc.value > 0: diff --git a/rpython/jit/backend/ppc/regalloc.py b/rpython/jit/backend/ppc/regalloc.py index 93419dfb87..f3ee1129e4 100644 --- a/rpython/jit/backend/ppc/regalloc.py +++ b/rpython/jit/backend/ppc/regalloc.py @@ -767,7 +767,7 @@ class Regalloc(BaseRegalloc, VectorRegalloc): def prepare_gc_store_indexed(self, op): base_loc = self.ensure_reg(op.getarg(0)) - index_loc = self.ensure_reg_or_any_imm(op.getarg(1)) + index_loc = self.ensure_reg(op.getarg(1)) value_loc = self.ensure_reg(op.getarg(2)) assert op.getarg(3).getint() == 1 # scale ofs_loc = self.ensure_reg_or_16bit_imm(op.getarg(4)) @@ -777,7 +777,7 @@ class Regalloc(BaseRegalloc, VectorRegalloc): def _prepare_gc_load_indexed(self, op): base_loc = self.ensure_reg(op.getarg(0)) - index_loc = self.ensure_reg_or_any_imm(op.getarg(1)) + index_loc = self.ensure_reg(op.getarg(1)) assert op.getarg(2).getint() == 1 # scale ofs_loc = self.ensure_reg_or_16bit_imm(op.getarg(3)) assert ofs_loc.is_imm() # the arg(3) should always be a small constant |