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author | 2021-04-20 13:53:10 +0100 | |
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committer | 2021-04-20 14:26:26 +0100 | |
commit | 60622b82a7a3517942ecdcd6dd0735abd3f567b1 (patch) | |
tree | 08dc05240174d363f479c270eabfc7e7d064c28f | |
parent | [AMDGPU] Use if instead of foreach in a few places. NFC. (diff) | |
download | llvm-project-60622b82a7a3517942ecdcd6dd0735abd3f567b1.tar.gz llvm-project-60622b82a7a3517942ecdcd6dd0735abd3f567b1.tar.bz2 llvm-project-60622b82a7a3517942ecdcd6dd0735abd3f567b1.zip |
[RISCV][NFC] Add tests for scalable-vector DAGCombiner improvements
These will all be improved by future patches.
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll | 11 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll | 12 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll | 27 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll | 26 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 25 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll | 25 |
6 files changed, 125 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll index 46d1f3c86488..e4a7ce1293dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll @@ -1107,3 +1107,14 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_2(<vscale x 8 x i64> %va) { ret <vscale x 8 x i64> %vc } +define <vscale x 8 x i64> @vor_vx_nxv8i64_3(<vscale x 8 x i64> %va) { +; CHECK-LABEL: vor_vx_nxv8i64_3: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, -1 +; CHECK-NEXT: ret + %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0 + %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer + %vc = or <vscale x 8 x i64> %va, %splat + ret <vscale x 8 x i64> %vc +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll index 1a4e2bd2e35b..d2a78ee5327d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll @@ -1079,3 +1079,15 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_2(<vscale x 8 x i64> %va) { ret <vscale x 8 x i64> %vc } + +define <vscale x 8 x i64> @vor_vx_nxv8i64_3(<vscale x 8 x i64> %va) { +; CHECK-LABEL: vor_vx_nxv8i64_3: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, -1 +; CHECK-NEXT: ret + %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0 + %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer + %vc = or <vscale x 8 x i64> %va, %splat + ret <vscale x 8 x i64> %vc +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll index 8f5c98555d3a..ba93b9b6964c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll @@ -102,6 +102,32 @@ define <vscale x 8 x half> @vfmerge_zv_nxv8f16(<vscale x 8 x half> %va, <vscale ret <vscale x 8 x half> %vc } +define <vscale x 8 x half> @vmerge_truelhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { +; CHECK-LABEL: vmerge_truelhs_nxv8f16_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: ret + %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0 + %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer + %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x half> %va, <vscale x 8 x half> %vb + ret <vscale x 8 x half> %vc +} + +define <vscale x 8 x half> @vmerge_falselhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { +; CHECK-LABEL: vmerge_falselhs_nxv8f16_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: ret + %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %va, <vscale x 8 x half> %vb + ret <vscale x 8 x half> %vc +} + define <vscale x 16 x half> @vfmerge_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %cond) { ; CHECK-LABEL: vfmerge_vv_nxv16f16: ; CHECK: # %bb.0: @@ -367,4 +393,3 @@ define <vscale x 8 x double> @vfmerge_zv_nxv8f64(<vscale x 8 x double> %va, <vsc %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> %splat, <vscale x 8 x double> %va ret <vscale x 8 x double> %vc } - diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll index 845b37e914b7..2808b17d28ba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll @@ -102,6 +102,32 @@ define <vscale x 8 x half> @vfmerge_zv_nxv8f16(<vscale x 8 x half> %va, <vscale ret <vscale x 8 x half> %vc } +define <vscale x 8 x half> @vmerge_truelhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { +; CHECK-LABEL: vmerge_truelhs_nxv8f16_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: ret + %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0 + %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer + %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x half> %va, <vscale x 8 x half> %vb + ret <vscale x 8 x half> %vc +} + +define <vscale x 8 x half> @vmerge_falselhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { +; CHECK-LABEL: vmerge_falselhs_nxv8f16_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 +; CHECK-NEXT: ret + %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %va, <vscale x 8 x half> %vb + ret <vscale x 8 x half> %vc +} + define <vscale x 16 x half> @vfmerge_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %cond) { ; CHECK-LABEL: vfmerge_vv_nxv16f16: ; CHECK: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll index 9b846e5d9ae0..0fbde8d00ae6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll @@ -777,3 +777,28 @@ define <vscale x 8 x i64> @vmerge_iv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 ret <vscale x 8 x i64> %vc } +define <vscale x 8 x i64> @vmerge_truelhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { +; CHECK-LABEL: vmerge_truelhs_nxv8i64_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: ret + %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0 + %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer + %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb + ret <vscale x 8 x i64> %vc +} + +define <vscale x 8 x i64> @vmerge_falselhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { +; CHECK-LABEL: vmerge_falselhs_nxv8i64_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: ret + %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb + ret <vscale x 8 x i64> %vc +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll index 5d6be54d8008..079ae398d621 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll @@ -749,3 +749,28 @@ define <vscale x 8 x i64> @vmerge_iv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 ret <vscale x 8 x i64> %vc } +define <vscale x 8 x i64> @vmerge_truelhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { +; CHECK-LABEL: vmerge_truelhs_nxv8i64_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: ret + %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0 + %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer + %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb + ret <vscale x 8 x i64> %vc +} + +define <vscale x 8 x i64> @vmerge_falselhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { +; CHECK-LABEL: vmerge_falselhs_nxv8i64_0: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 +; CHECK-NEXT: ret + %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb + ret <vscale x 8 x i64> %vc +} |