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| author |   Jay Foad <jay.foad@amd.com> | 2021-04-20 14:19:51 +0100 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2021-04-20 14:20:30 +0100 |
| commit | 2aea830ec432ab1732bbcfb14a3bd77d200dbf5f (patch) | |
| tree | 17861959025e526390d908858857e29712e1e137 | |
| parent | [flang][nfc] Port 2 tests to use the new driver when enabled (diff) | |
| download | llvm-project-2aea830ec432ab1732bbcfb14a3bd77d200dbf5f.tar.gz llvm-project-2aea830ec432ab1732bbcfb14a3bd77d200dbf5f.tar.bz2 llvm-project-2aea830ec432ab1732bbcfb14a3bd77d200dbf5f.zip | |
[AMDGPU] Use if instead of foreach in a few places. NFC.
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MIMGInstructions.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index e438394c18e4..f8d08c641598 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -317,7 +317,7 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, if op.HAS_BASE then { def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, !if(enableDisasm, "AMDGPU", "")>; - foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in + if !not(ExtendedImageInst) then def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32, !if(enableDisasm, "GFX90A", "")>; def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32, @@ -328,7 +328,7 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, let VAddrDwords = 2 in { if op.HAS_BASE then { def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>; - foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in + if !not(ExtendedImageInst) then def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64>; def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>; def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>; @@ -338,7 +338,7 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, let VAddrDwords = 3 in { if op.HAS_BASE then { def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>; - foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in + if !not(ExtendedImageInst) then def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96>; def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>; def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>; @@ -348,7 +348,7 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm, let VAddrDwords = 4 in { if op.HAS_BASE then { def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>; - foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in + if !not(ExtendedImageInst) then def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>; def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>; def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4, @@ -786,7 +786,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm, def _V # addr.NumWords : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass, !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>; - foreach _ = BoolToList<!eq(ExtendedImageInst, 0)>.ret in + if !not(ExtendedImageInst) then def _V # addr.NumWords # _gfx90a : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass, !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index b00ed56126c1..095fceae609c 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -955,13 +955,13 @@ multiclass SIRegOperand64 <string rc, string MatchName, string opType, let ParserMatchClass = RegImmMatcher<MatchName#"F64">; } - foreach _ = BoolToList<Vectors>.ret in + if Vectors then def _v2f32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { let OperandType = opType#"_V2FP32"; let ParserMatchClass = RegImmMatcher<MatchName#"V2FP32">; let DecoderMethod = "decodeOperand_VSrcV232"; } - foreach _ = BoolToList<Vectors>.ret in + if Vectors then def _v2b32 : RegisterOperand<!cast<RegisterClass>(rc#rc_suffix)> { let OperandType = opType#"_V2INT32"; let ParserMatchClass = RegImmMatcher<MatchName#"V2INT32">; |